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smx® is an advanced, hard real time RTOS kernel for embedded systems. It has been toughened by 30 years of use in hundreds of embedded applications. smx supports ARM/Cortex, ARM-M/Cortex-M, ColdFire, and other processor architectures, and can be used by itself or with other modules of the SMX RTOS.

The primary API is C, but a C++ kernel API is available in smx++.

smx reduces development schedule and cost by offering proven code and pre-integration with popular processors and tools. The smxBSP package, which is included with smx, provides processor-specific support for smx and for the application software. smx is shipped with project files and documentation for specific tool suites. Clear manuals help users to understand how to use multitasking in their designs. The smx Protosystem allows a quick start, with good examples.

smx lowers product cost due to its high performance and small size. High performance allows using less expensive processors and smaller memories. In some cases, it allows using a single processor instead of a dual-processor. In many cases, smx fits into on-chip RAM and flash. This eliminates the need for external memory chips and may allow using processors without processor buses, which reduces pin count and thus cost, even further.

smx helps to improve reliability because it offers proven code, extensive built-in diagnostics, and powerful kernel-aware debugging using smxAware. The smxAware DLL works with several debuggers to provide kernel-aware debugging. It also offers Graphical Analysis Tools, which include, for example, timelines that show when each ISR, LSR, and task ran and what caused it to start and stop running. It shows stack, memory, and other resource usages, as well as a graphical view of memory layout that can be zoomed. This kind of support permits delivering reliable embedded systems on tight schedules.

More easily maintained application code results from the better structure imposed by smx. Applications based upon smx are organized into tasks that behave predictably. This is more appropriate for modern embedded systems than is the customary super loop, which often results in spaghetti code. Embedded systems written with smx are easier to understand, debug, and maintain. The task structure provided by smx makes it easier to add new product features to keep up with competition.

smx is affordable There are no royalties, and the up-front cost is low. Full source code and 3 months of support are included.

High performance is one of the key features of smx. A unique three-level control structure (ISR/LSR/Task) permits optimum control. ISRs respond to hardware interrupts and reenable them as quickly as possible. LSRs  perform deferred interrupt processing, with interrupts enabled. Less urgent processing is done by tasks. All smx calls operate with interrupts enabled. The smx scheduler disables interrupts only briefly. Because of this structure, smx interrupt latency is extremely low (comparable to that of the processor, itself). In addition, LSRs, which are invoked by ISRs and smx timers, provide much faster switching times than tasks because they do not save context and they do not switch stacks. Finally, the unique smx layered ready queue provides fast and deterministic task switching.

Small size is another key feature of smx. RAM usage has been optimized, as well as code size. By fitting into on-chip SRAM and flash, not only is the cost of external memory avoided, but also performance is greatly increased, thereby allowing a less expensive processor to be used. Support for one-shot tasks that can share stacks, minimizes stack RAM. Control blocks are small to also save RAM. smx code is efficiently written to minimize code footprint.

Advanced Features:   See smx Datasheet and smx Special Features.

Versions Offered:   ARM, Cortex, ColdFire

To learn more about the smx multitasking kernel see:

  1. smx Datasheet
  2. smx Special Features
  3. smx Philosophy
  4. smx v5
  5. smx++ Datasheet
  6. Link Service Routines
  7. One-Shot Tasks
  8. Deferred Interrupt Processing
  9. Other Articles

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  • Reduces dev schedule and cost
  • Lowers product cost
  • Improves reliability
  • More easily maintained app code
  • Is affordable

Brief History of smx

The smx multitasking kernel was first shipped in Jan 1989, for use on x86 real-mode processors. At that time, memory and processors were at least two orders of magnitude smaller and slower than they are today. Consequently, smx was designed to be very simple and to offer high performance with a small memory footprint. In 1996, the smx scheduler was rewritten in C, and smx was ported to the PowerPC. It was ported to ColdFire in 1999, ARM in 2002, and ARM-M in 2008. smxBSP was introduced in 2003 to make supporting new processors easier. In Oct 2010, v4.0 was released, which had many global naming, cleanup, and structural changes. The API was modernized and the scheduler was reimplemented. In the years since, successive v4.x releases made significant improvements to each area of smx. In Jul 2019, v5.0 was released with a focus on security using a memory protection unit (MPU) to partition the RTOS and app. v4 and v5 changes are summarized on our About v5 page. The services provided by smx have more than doubled; yet it is still small and fast compared to other solutions. smx has evolved from simple to superior and now secure.

Achieving Low Interrupt Latency

Link Service Routines (LSRs) link foreground ISRs with background tasks. The goal is for each ISR to do the minimum work necessary to get or put a datum, reset the peripheral, and reenable the interrupt. ISRs invoke LSRs to do deferred interrupt processing and to perform smx calls that cause tasks to run.

smx was designed to minimize interrupt latency. Because smx calls can be made only from LSRs, there are no critical sections to protect in them nor in 98% of the scheduler (i.e. almost all of smx!). All of this code runs with interrupts fully enabled. Only a few small sections of the scheduler disable interrupts (e.g. 58 clocks for smxCF). As an added bonus, LSRs permit dealing with peak interrupt loading in a smooth manner. For more information, see: Link Service Routines.

Saving SRAM
with One-Shot Tasks

On-chip SRAM is much faster than external SDRAM. However, it is precious. In multitasking systems, a major usage of RAM is for task stacks. To mitigate this problem, smx supports one-shot tasks. These run once from start to finish. When done, no information is carried over to the next run. Hence, a one-shot task does not need a stack when it stops. smx allows the stack to be released back to a stack pool, for use by another task. Under smx, stopped tasks can wait at semaphores, mutexes, exchanges, etc � just like normal suspended tasks. When a one shot task is dispatched, the smx scheduler gives it a new stack from the stack pool. Hence, a system with 10 tasks could operate with only 2 stacks as long as only 2 tasks need to run simultaneously. If no stack is available, the task waits. smx permits any mix of one-shot tasks and normal tasks. For more information, see One-Shot Tasks.
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