1. Link Service Routines. LSRs provide a good mechanism for deferred interrupt processing, low-jitter timer operations, and other very-high priority processing. They cannot be blocked by tasks and so avoid priority inversion problems. LSRs enable smx to have ultra-low interrupt latency.
2. Graphical Analysis Tools for smxAware. The event timeline display shows when all tasks, LSRs, and ISRs ran and what smx calls occurred in each. The display can be zoomed in to show as much detail as needed. The stack usage display shows stack usage per task and alerts of near and actual overflows. The CPU usage display show % time used by each task, LSR, and ISR.
3. One-Shot Tasks. smx supports both normal and one-shot tasks. One-shot tasks share stacks from a common pool and release them back to it when done. This can greatly reduce RAM usage and also may permit using on-chip SRAM for task stacks, thereby achieving much higher performance.
4. Multiple tasks per priority level. smx permits tasks to share the same priority and it dispatches the longest waiting task at the current top priority level to run first. This is a more natural scheduling algorithm than one task per priority.
5. Layered ready queue. smx has a separate queue per priority level. Scheduling is a fast two step process (index to the level and link to its end) regardless of how many tasks are in the ready queue.
6. Mutexes. Because smx permits tasks to share priority levels, it has a more efficient scheme of priority inheritance promotion that boosts the current mutex owner only as high as the highest priority waiting task. In addition smx implements priority promotion propagation between mutexes to prevent unbounded priority inversion when multiple mutexes must be tested. smx mutexes also implement priority ceiling promotion, which is necessary for Deadline Monotonic Analysis. Finally, smx mutexes permit a combination of  promotion schemes for optimum performance and safety.
7. Unlimited number of tasks: smx is designed to support a very large number of tasks efficiently.
8. Versatile Messaging. smx allocates a Message Control Block (MCB) per message, which contains the following information and has the following advantages:
1. Protected data pointer. The MCB must be valid and the data pointer always points to the start of the message. It cannot be left pointing to the middle or end, due to a programming error.
2. Size helps to control overrun errors.
3. Owner prevents memory leaks when owners are deleted, by deleting messages they own.
4. Priority allows more important messages to be passed around less important messages.
5. Priority Pass. Pass exchanges permit a message priority to be passed to a receiving task. Thus a server task can automatically adopt the same priority as the client task that it is serving.
6. Reply address tells a server task where to send a response or processed message.
7. Return pool tells where to send a message no longer needed.
8. Forward and backward links allow MCBs to be linked into exchange lists. Hence message queues may be of any length.
9. Exchanges. Messages are sent to and received from exchanges. Exchanges allow messages to wait for tasks or tasks to wait for messages. The latter is useful to control access to shared resources. Messages can contain resource information such as port numbers, keys, passwords, sizes, etc.
10. Event Tables. These permit tasks to wait for the AND or OR of up to 31 events. Different tasks can wait for different combinations of the same events.
11. Event Queues permit an efficient way for tasks to wait for specified numbers of events (e.g. ticks). Only the counter in the first TCB in the queue is decremented for each event, for efficiency.
12. Dynamically Allocated Regions. Modern embedded systems have many kinds of RAM: on-chip SRAM, off-chip SRAM, DRAM, non-cached RAM, cached RAM, system RAM, application RAM, etc. DARs help to manage this complexity more easily.
13. Low Jitter Timers. smx provides both one-shot and cyclic timers. These are useful for timeouts and for triggering repetitive operations. Because smx timers directly invoke LSRs when they time out, timer code runs ahead of all tasks and is immune to priority inversions. Since LSRs can be interrupted only by ISRs, which should be short, timer jitter is minimal.
14. Error Detection. smx monitors about 80 error types. It provides for point of occurrence error handling and central error handling. The smx error management system includes an error buffer, error counters, error service routines, and error message display functions.
15. Excellent Manuals. smx offers very detailed and complete manuals. There are four up-to-date manuals: User’s Guide, Reference Manual, Target Guide, and Quick Start. The User’s Guide is like a tutorial book. The other manuals go into greater detail.

Please contact me with any comments or questions about this article.

Ralph Moore
ralphm @ smxrtos.com
smx Architect
Micro Digital Inc

9/4/08

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